Communication mechanism for data transfer and control between data processing systems and subsystems

ABSTRACT

Apparatus for establishing and maintaining communication between a number of different types of subsystems of a data processing system. The apparatus contains elements which are subsettable with respect to the various functions which are performed depending upon the characteristics of each of the subsystems which are connected together. One function is that of attaching process control devices to a central processing unit. These devices are characterized by having simple interfaces, by involving non-terminating operations, by having high storage access rates and by time dependencies. A further function is that of inter-CPU signalling involving the transfer of small amounts of information. A further function is that of sharing main storage between a CPU and a subsystem element. The communication apparatus is comprised of two separate and functionally independent logical elements. The first is an external main storage adapter which performs the function of sharing storage between the central processing unit and a subsystem element. The second logical unit is the control adapter which provides the physical and logical connection between the subsystem units. The control adapter attaches to a control interface which contains a polling mechanism, a selection mechanism, a general bus, and several interlocked communication tag lines. A control transfer sequence is defined by the interface such that each attached subsystem may initiate communication with any other attached subsystem. A polling mechanism allocates temporary control of the interface to a unit desiring to initiate communication. A selection mechanism allows selective subsystem-to-subsystem communication.

Moore et al.

[ Apr. 2, 1974 Primary ExaminerRaulfe B. Zache Attorney, Agent, orFirm-Owen L. Lamb ABSTRACT Apparatus for establishing and maintainingcommunication between a number of different types of subsystems of adata processing system. The apparatus contains elements which aresubsettable with respect to the various functions which are performeddepending upon the characteristics of each of the subsystems which areconnected together.

One function is that of attaching process control devices to a centralprocessing unit. These devices are characterized by having simpleinterfaces, by involving non-terminating operations, by having highstorage access rates and by time dependencies.

A further function is that of inter-CPU signalling involving thetransfer of small amounts of information.

A further function is that of sharing main storage between a CPU and asubsystem element.

The communication apparatus is comprised of two separate andfunctionally independent logical elements. The first is an external mainstorage adapter which performs the function of sharing storage betweenthe central processing unit and a subsystem element. The second logicalunit is the control adapter which provides the physical and logicalconnection between the subsystem units. The control adapter attaches toa control interface which contains a polling mechanism, a selectionmechanism, a general bus, and several interlocked communication taglines. A control transfer sequence is defined by the interface such thateach attached subsystem may initiate communication with any otherattached subsystem. A polling mechanism allocates temporary control ofthe interface to a unit desiring to initiate communication. A selectionmechanism allows selective subsystem-to-subsystem communication.

4 Claims, 35 Drawing Figures CPU 1 TRsTRucTTTTR MAIN ExEcuTER STERAGE T12 CONTROL EXTERNAL RATR EXTERNAL RATR A ADAP ER sT0RAcE ADAPTERAnAPTERTm sToR GE 1 BASIC CHANNEL l TRTERTAcE AND ,25 29 TRTERTAcE 25ADAPTERS j 2e CONTROL RAsTER' cTTTTTRnL mm 2/ AT1APTER (t) ABAPTER24/ADAPTER l2) ADAPTER suB-sTsTER suB-sTsTER -18 F I G 3 PATENTEDAPR21914 3.801.962

WET 01 [If 22 F l G. 1

INSTRUCTION MAIN ExEcuTER sTDRAcE I coRTRDE EXTERNAL TAATR ExTERRAE RAID20 ADAPTER (0) sTDRAcE ADAPTER sTDRAcE ADAPTER BASIC CHANNEL 27IRTERTADE ADD 2 5 /25 29 INTERFACE ADAPTERs CONTROL TAAsTER CONTROLATAsTER 22 ADAPTER m ADAPTER 24/ADAPTER(2) ADAPTER sua- SYSTEMsuD-svsTETA -18 EXTERNAL MAIN MASTER ADAPTER sTDRADE ADAPTER DATA BUS WT R D D R T l INBOUND LINES L06 0 LOGIC LOGIC Q Eb OUTBOUND LINES jgPATENTEDAPR 21914 3,801,962

SHEET 03 0F 22 FIG.4 CONTROL memos 64 0mm BUS I8 LINES I GENERAL BUSBITS P0,0,1,---T,P1,8,9,---I5 [66 INTERRUPTION REQUEST BUS II6'LINES)PRIOR NTERRUPTION REQUEST LEVEL "-15 I/U RUPTION REQUEST LEVELS ""T fTAG LINES CONTROL LIST CONTROL comm ADAPTER SELECTION uses l 0 T mm o, 12 3 ACTIVE um RES MALFUNCTION SIGNALS EOUENCE RESET ESET PATENTEDAPR21974 3.801.962

saw on or 22 F l G. 5 E x T E RNAL MAIN STORAGE INTERFACE 44 DATA BUSDATA Bus ans Po,o,1,--- 6,7, P1,8,9,---14 45,P3J6.17."-, 22,23.-".P8,

s A STORAGE ADDRESS BUS STORAGE ADDRESS1BUS ans P0 o,1,---e,1, PT, 8

s 4 KEY BUS KEY BUS ans P,0 1 2 ,3

50 EXTERNAL MASTER MAIN ADAPTER MARK BUS STORAGE MARK BUS ansP,0,1,2,3.4.5.6.7 ADAPTER 52 DATA- TRANSFER CHECK BUS DATA- TRANSFERCHECK BITS P,U,1,2

54 TAC LINES P TENTEBAPR 2|974 3.801.962

SHEET U5 0F 22 F|G 6 CONTROL ADAPTER LOGIC CIRCUlT (CPU,UNIT 0) GATEFUNCTION CODE To GEM. BUS (SIGP 0R 1/0 TMsTRuGTmM) m5 GATE PARAMETERBYTES 0.1 T0 GEM BUS(SIGP) 0 w GATE I/F ADDRESS T0 GEM BUS [I/OINSTRUCTION) I GMTR UNIT 0 ACTIVE a DRIVER GATE PARAMETER BYTES P3 T0GEN BUS (SIGP) GATE EMMGTTGM CODE T0 GEM BUS(PIOR T/o INTERRUPT.ACCEPT.) O m GATE DEVICE ADDRESS To GEM BUS (1/0 :MsTRuGTmM) L EAsT l RM CONTROL sTATMs SUMMARY AGGEPTEG (PI AGGEPTAMG E) PARAMETER BYTES 0,1AGGEPTED (PI ACCEPTANCE) DEVICE ADDRESS ACCEPTED (I/O |NTERRU- PTlONAGGEPTAMGE) 0 UP ADDRESS ACCEPTED (1/0 INTERRUPF ION AGGEPTAMGE) P aDRIVER sTATMs BYTEs 2,3 ACCEPTED (SIGP) PARAMETER BYTES 2,5 AGGEPTED (PIACCEPTANCE) CONDITION CODE AGGEPTEDTI/G INSTRUCTION) 0 STATUS SUMMARYACCEPTED (1/0 TMTER- RUPTION) a DRIVER mp PATENTETITIPR 2 IBTI 3.801.962

SHEET 05 0F 22 FIG. 7

FUNCTION CODE REG BIT P0 I GENERAL Bus GATE FUNCTION CODE To GEN BUSPARAMETER REG BIT P0 GATE PARAMETER BIITEs 0,I T0 GEN Bus PARAMETER REGBIT P2 GATE PARAMETER BTTEs 2,3 T0 GEN Bus o a m 1/0 ABBREss REG BIT P0l '3 GATE I/F ADDRESS To GEN BUS 1/0 ABBREss REG BIT P2 I GATECHANNEL-DEVICE ADDRESSTO GEN BUS IIMIT 0 ACTIVE FUNCTION CODE REG BIT I5I BATE FUNCTION CODE T0 GEN Bus PARAMETER REG BIT I5 GATE PARAMETERBYTES 0,I To GEN BUS PARAMETER REG BIT 34 I BATE PARAMETER BYTEs 2,5 ToGEN BUS O a I/II ADDRESS REG BIT I5 I W GATE I/F ABBREss T0 GEN BUS I/OADDRESS REG BIT 3T GATE CHAN-DEVICE ABBREss T0 GEN Bus UNIT I AcTIvE FIG8 POLLING UNIT IT HAS POLL 1 RESPONSE UNIT 0 AcTIvE a D SELECT OUT I IPOLLING RERuEsT IIMIT O RERIIIREs POLL I a D DESELECT I I a O D SELECTouT SELECT IN URGENT cIIIIITIITIoIII I a h a a D IURGENTPOLUNG POLLINGREBuEsT I i |RE0 URGENT POLLING O A a D iDESELECT REQ PAIENIENIIPII 2I974 3.801.962

SNEEI 07 0f 22 FIG. 90

cIIEcN STOP STATE I MALFUNCTION ALERT I FIG. 9b sEIIIIENcE ERRORSEQUENCE RESET ANY TAG LINE IN a FIG. 9c RESET INTERFACE .PULSE 5 ANRESET D R LATCH OFF 5 ON & ANY OTHER I S LATCH I R UNIT & I ACTIVE DLY 1UNIT 0 ACTIVE FIG. 10

UNIT ACTIVE LINES IINII o HAS POLL INTERFACE cIINNIINIcAIIIIN sEIIIIENcEUNIT I ACTIVE SELECT IINII o A L I m I UNIT n ACTIVE SELECT UNIT A &

UNITn +I AcIIvE SELECT UNIT A I A J: l UNIT m ACTIVE SELECT IINII m KIPAIENTEDAPR 2 1974 SHEET 08 0F 22 FIG." INTERFACE ADAPTER LOGIC(ATTACHED UNIT, UNIT 4) GATE STATUS SUMMARY T0 BUS (SIGP) GATE PARAMETERBYTES o,I To GEM GusIPT AGGEPTI GATE I/F ADDRESS T0 GEM BUS (1/0 INT)DLY a w GATE CHANNEL DEVICE ADDRESS To GEN BusIT/o INT) UNIT I AGTIvEGATE STATUS To GEM BUS (SIGP) GATE PARAMETER BYTES 2,3 To GEM BUS (PIACCEPT) GATE CONDITION CODE To GEM BUS (1/0 IIIsTI our a L ST GATEsTATus sIIMMARY T0 GEIII BUS (I/O INTRPT.) F CONTRQL TGMGTIGII CODEACCEPTED (SIGP 0R I/O) PARAMETER BYTES 0,1 AGGEPTEG PROCEED I/F AGGREssACCEPTED 8 PARAMETER BYTES 2,5 AGGEPTEG TIEvIGE ADDR ACCEPTED STOPTGIIGTIGM CODE AGGEPTETIIT/o INT. 0R PI) a IIMIT I BUSY a BUSY UNIT IRESPONSE PAIENIEDAPR 2 I974 3.801.962

SHEET 09 HF 22 sTATus REG BIT P2 FIG. 20

GATE STATION REG To GEM BUS &

STATUS suMMARY REG BIT P0 GATE sTATus SUMMARY To GEM BUS I PARAMETER REGBIT P0 GATE PARAMETER BYTES 0,4 To GEN BUS I PARAMETER REG BIT P2 & GENBUS GATE PARAMETER GYTEs 2,3 T0 GEM BUS BIT P0 I I CONDITION CODE REGBIT P0 GATE CONDITION CODE T0 GEN BUS M i 1/0 ADDR REG BIT P0 GATE I/FADDRESS To GEN BUS i l 1/0 ADDR REG BIT P2 I GATE CHANNEL DEVICE ADDR T0GEN BUS 1 GEM BUS P BIT I5 FIG. 12b

PRIORITY INTERRUPTIDN REGuEsT D PRIORITY TMTERRGPTTGM REG LEVEL 0REGuEsT LEVELO LEVEL 45 D PATENTEUAPR 2mm 3.801.962

sum 10 0F 22 FIG. 130 MAIN STORAGE ADAPTER OLY GATE DATA TO DATA BUSFETCH REQUEST A MAIN STORAGE SEQUENCE A MAIN STORAGE CHECKS STORESEQUENCE COMPLETE FIG. 5 5

GATE CHECKS TO CHECK BUS DH MAIN STORAGE SEQUENCE A MAIN STORAGE CHECKSOATA XFER CHECK A STORE REQUEST A FETCH REQUEST A ACCEPTED BUSINFORMATION BUS RESPONSE A SEQUENCE A FlG.13c

GATE OATA TO DATA BUS DATA BUS BIT PO OATA BUS REG BIT PO F'G DATA BUSBIT 63 GATE CHECKS To CHECK BUS CHECK BUS an F CHECK BUS REG BIT P l I 0M RESPONSE A PATENTEDAPR 2IB74 3. 01 5 SHEET 11 F 22 MASTER A DAPTERCIRCUITS GATE INFORMATION TD BussEs FOR A SEQUENCE GATE INFORMATION ToBUSSES FOR B SEQUENCE KEY BUS BIT P KEY BUS REG BIT P D T I I KEY BUSREG BIT i I KEY Bus BIT 5 T l* sAD REG B IT P0 3L 1 SAB BIT PD A SAB REGBIT Q I SAB BIT sTDRE ASEQUENCE WM 8 SEQUENCE DATA BUS BIT P0 DATA BUSREG BIT P0 8 D DATA BUS R'Ec BIT MARK BUS REG BI T P IIARII Bus RED BITT MARK Bus BIT T STORE REQUEST A FIG.I5 ms sTDRE A SEQUENCE DLY DATAxTER REsPoIIsE A O I J- DATA XFER CHECK A AccEPTED A SEQUENCE a CHECK INDICATIDNS 65NS FETCH A sEouEIIcE DLY C I ACCEPTED A sED. DATA O I DAT AXFER CHECK A ACCEPTED A SEQUENCE CHECK INDICATIONS FETCH REQUEST APAIENTEUAPR 21914 3.801.962

SHEET 12 0F 22 FIGJG POLLING PAIENTEDAPR 21974 3.801.982

SHEET 13 CF 22 FIG.47

POLLING (CONTINUED) PASS THE FULL INITIATE POLLING SEQUENCE RAISE SELECTOUT RAISE SELECT OUT DROP SELECT OUT 2I2 DROP SELECT OUT FIGI6PATENTEDAPR 2 I974 F l (5. I8

SHEET l OF 22 CONTROL TRANSFER SEQUENCE I SIGNAL PROCESSOR I INITIATINIT RA T ACT OWN LI OF 0 ACTIVE LINE AND THE UNIT WHICH GATE PARAMETERBYT O,I TO GEN BUS GATE PARAMETER s 2,3 TO GEN PROCEED RESET CONTROLSRAISE PROCEED RESET CEN BUS PROCEED RESET PROCEED RAISE LAST CONTROLPAIENIEDAPR 2:914 3.801.962

sum 15 ur 22 GATE smus REG ems 2,3 T0 GEN BUS DELAY 65NS FIG.49

ACCEPT INFORMATION ON GEN BUS RAISE STOP RESET GEN BUS RESET LASTCONTROL RELEASE POLL PATENTEU PR 2I9T4 SHEET 160? 22 FIG.20.

PRIORITY INTERRUPTION INITIATING UNIT RAISES ITS OWN UNIT ACTIVE LINE AUNIT ACTIVE LINE OF THE OTHER UNIT GATE FUNCTION OOOE TO GEN BUS DELAY65NS I RESET LAST CONTROL PAIENIEDAPR 2 \GTA FIG.24

SHEET 17 HF 22 [596 GATE ORB SUMMARY GATE PARAMETER BYTES GATE PARAMETERBYTES T0 GEN BUS 0,4 To GEN BUS 2,3 To GEN BUS T A T DELAY 65 NS DELAY65 N8 572 593 I TR RA sE CON 0L \m 400 RAISE LAST CONTROL 576 402 N0 NOYES YES ACCEPT INFORMATION T ACCEPT INFORMATION 578 0N GEN BUS 0N GENBUS T T RAISE PROCEED 406 RAISE sToP 580 YES YES RESET GEN BUS REsET GENBUS 584 440 RESET CONTROL I 586 I /{RESET LAST CONTROL I 412 44a REsETSTOP FTG AG STOP YES PATENTEDAPR 2 I974 SIIEET 18 OF 2.2

FIG.22

DATA TRANSFER SEOUENCE FETCH YES MASTER UNIT GATE STORAGE PROTECTION KEYTO KEY BUS MASTER UNIT GATE STORAGE ADDRESS TO ADDRESS BUS STORE [448MASTER UNIT DELAY 65 NS MASTER UNIT GATE DATA BYTES T0 DNA BUS MASTERUNIT GATE MARK BITS TO MARK BUS MASTER UNIT DELAY 65 NS MASTER UNITRAISE STO REG A I 456 PATENTEU R SHEET 19 RE 22 ADAPTER GATE sTATDs BITS266 T0 cREcA BUS ADA TER MASTER UN IT SAMPLES DHEcA BUS ADAPTER GATEDATA ADAPTER DELAY s5 Rs 276 TD DATA BUS ADAPTER DELAY 5 R5 ADAPTERRAISE DT OK A M Rs A 278 2T0 DT CK A MASTER UNIT SAMPLE DATA BUS zae VMASTER UNIT RE Ts INPUTS TD AEY, ADDREss, MARK A BUSSES, IF ANY 288MASTER UNIT RESET 3T0 REG A OR FOR REG A

1. A data processing system comprising: a plurality of subsystems; acontrol transfer interface; a data transfer interface logicallyindependent of said control transfer interface; means for connectingsaid subsystems to said control interface in a multi-dropped closedloop; means for connecting said subsystems to said data transferinterface point-to-point; a polling mechanism in each subsystem andassociated with said control transfer interface for allocating temporarycontrol of said control interface to A subsystem desiring to initiatedata transfer over said data transfer interface.
 2. A data processingsystem comprising: a plurality of subsystems; a control transferinterface; a data transfer interface; means for connecting saidsubsystems to said control interface in a multi-dropped closed loop;means for connecting said subsystems to said data transfer interfacepoint-to-point; a polling mechanism in each subsystem and associatedwith said control transfer interface for allocating temporary control ofsaid control interface to a predetermined subsystem desiring to initiatedata transfer over said data transfer interface, and means in saidpredetermined subsystem for sequencing said control transfer interfaceto effect transfer of program specifiable control initiating order codeinformation and associated return transfer of either acceptance orspecific plural bit exception status indications to said predeterminedsubsystem.
 3. Apparatus for establishing and maintaining communicationbetween a number of different types of subsystems in a data processingsystem comprising: a control interface including information sources andtag control lines interconnecting said subsystems in a multi-droppedclosed loop; polling means associated with each subsystem interactingwith said tag control lines of said control interface for relegating toa particular subsystem the logical state of the master subsystem, in amaster/slave relationship with others of said subsystems; selectionmeans in said particular subsystem associated with said controlinterface tag control lines for initiating a control transfer sequenceover said control interface, to thereby prepare one of said slavesubsystems to send or receive data to or from said master subsystem; anexternal main storage interface interconnecting said subsystemspoint-to-point; and means in said particular subsystem for initiating adata transfer sequence over said external main storage interface. 4.Apparatus for establishing and maintaining communication between anumber of different types of subsystems in a data processing systemcomprising: a control interface including information sources and tagcontrol lines interconnecting said subsystems in a multi-dropped closedloop; selection means in a particular subsystem associated with saidcontrol interface for initiating a control transfer sequence to transfercontrol information over said information sources of said controlinterface, to thereby select and prepare one of said subsystems to sendor receive data to or from said particular subsystem; an external mainstorage interface interconnecting said subsystems point-to-point; meansfor initiating a data transfer sequence over said external main storageinterface; and a polling mechanism associated with said tag controllines for allocating temporary control of said control interface to saidparticular subsystem, whereby said particular subsystem may initiatecommunication with said one of said subsystems.